1. Field
The embodiments discussed herein relate to an interface.
2. Description of Related Art
Memories may include static random-access memory (SRAM) having a static memory cell including six transistors, a dynamic random-access memory (DRAM) having a dynamic memory cell including one transistor and one capacitor, etc. The DRAM accommodates a larger number of memory cells because a memory cell area of the DRAM is smaller than that of the SRAM. A refresh operation is performed in the DRAM because charge accumulated as data on the capacitor is reduced in the form of a leakage current.
A pseudo SRAM is a DRAM having a self-refreshing function. In response to a refresh command input, an address of a memory cell to be refreshed is automatically generated and the refresh operation is performed.
Related techniques are disclosed in Japanese Laid-open Patent Publication No. H63-275095, and Japanese Laid-open Patent Publication No. 2002-140890.